This invention relates generally to light emitting diodes and more specifically to contacts for light emitting diodes.
Semiconductor light emitting devices such as light emitting diodes (LEDs) are among the most efficient light sources currently available. Material systems currently of interest in the manufacture of high brightness LEDs capable of operation across the visible spectrum include group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials; and binary, ternary, and quaternary alloys of gallium, aluminum, indium, and phosphorus, also referred to as III-phosphide materials. Often III-nitride devices are epitaxially grown on sapphire, silicon carbide, or III-nitride substrates and III-phosphide devices are epitaxially grown on gallium arsenide by metal organic chemical vapor deposition (MOCVD) molecular beam epitaxy (MBE) or other epitaxial techniques. Often, an n-type layer (or layers) is deposited on the substrate, then an active region is deposited on the n-type layers, then a p-type layer (or layers) is deposited on the active region. The order of the layers may be reversed such that the p-type layers are adjacent to the substrate.
Some of these substrates are insulating or poorly conducting. In some instances, a window is attached to the semiconductor layers to enhance optical extraction. Devices fabricated from semiconductor crystals grown on or affixed to poorly conducting substrates must have both the positive and the negative polarity electrical contacts to the epitaxially grown semiconductor on the same side of the device. In contrast, semiconductor devices grown on conducting substrates can be fabricated such that one electrical contact is formed on the epitaxially grown material and the other electrical contact is formed on the substrate. However, devices fabricated on conducting substrates may also be designed to have both contacts on the same side of the device on which the epitaxial material is grown so as to improve light extraction from the LED chip. There are two types of devices with both the p- and n-contacts formed on the same side. In the first (also known as the flip chip), the light is extracted through the substrate or window material. In the second (also known as an epi-up structure), the light is extracted through the contacts, through the uppermost semiconductor layers of the device, or through the edges of the devices.
In accordance with one embodiment of the invention, a light emitting device includes a substrate, a layer of first conductivity type, a light emitting layer, and a layer of second conductivity type. A plurality of vias are formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, diffusion, or selective growth of at least one layer of second conductivity type. A set of first contacts electrically contacts the layer of first conductivity type through the vias. A second contact electrically contacts the layer of second conductivity type. In some embodiments, the area of the second contact is at least 75% of the area of the device. In some embodiments, the vias are between about 2 and about 100 microns wide and spaced between about 5 and about 1000 microns apart. In some embodiments, the vias are formed in a square array, a hexagonal array, a rhombohedral array, or an arbitrary arrangement.
A light emitting device according to the present invention may offer several advantages. First, since the distance over which current must laterally spread within the semiconductor is reduced, the series resistance of the device may be reduced. Second, more light may be generated and extracted from the device since the area of the active region and the area of the second contact are larger than a device with a single first contact. Third, the invention may simplify the geometry of the interconnections between the device and the submount, enabling the use of, for example, low cost solder deposition methods.
In one embodiment, the first contacts are connected by a set of interconnects. An insulating layer is formed over the device. On one portion of the insulating layer, openings aligned with the second contacts are made in the insulating layer. On another portion of the insulating layer, openings aligned with the first contacts and the interconnects are made in the insulating layer. A first layer of a submount connection material such as solder is deposited on one portion of the device and a second layer of submount connection material is deposited on the other portion of the device. The two submount connection layers can then be used to connect the device to a submount.